Power consumption has become an important optimization metric in the design of micro-electronic circuits. Optimizing the power consumption may be achieved at various abstract levels of design, from algorithmic and system levels down to layout and circuit levels. Typically, power optimization techniques applied at the higher abstract levels have a higher potential for saving power. Particularly, power optimization techniques and/or modifications applied at the register-transfer level (RTL)—where the system is conceptualized in terms of registers and data transfers—may save a substantial amount of power.
For example, turning to FIG. 1, a circuit 1 having a register bank 50, coupled to a clock signal, that takes the result 45 of a multiplier 40 as its only input is shown at the RTL. The multiplier 40 has two inputs, x and y. The inputs and signals are digital and thus, will have either ON or OFF (1 or 0) values, or a combination thereof. In this circuit, there are two enable signals, en1 and en2, coupled together by an AND gate 10 to produce a resulting signal 15, and the register bank 50 will only load the result 45 of the multiplier 40 when the resulting signal is ON, i.e., when both enable signals, en1 and en2, are ON.
During the clock cycle, when the register bank 50 is not loading the result 45, i.e., when either en1 or en2 are OFF, the power dissipated by the multiplier 40 is wasted. This waste may be significant because the multiplier 40 typically consumes a substantial amount of power. One possible solution is to apply a power saving technique and/or modification known in the art called “sleep-mode transformation,” wherein the multiplier 40 and its input data paths, x and y, are shutdown when its outputs 45 are not used. This may be achieved by coupling the resulting signal 15 with the inputs, x and y, via two banks of AND gates, 20 and 30. Thus, the inputs, x and y, will be loaded into the multiplier 40 only when the resulting signal 15 is ON and the register 50 is enabled to load the results 45 of the multiplier 40.
Micro-electronic circuits, such as the circuit above, may be developed using a high-level language, such as the Very High Speed Integrated Circuit Hardware Description Language (VHDL). Further, there are several commercially available tools such as Electronic Computer-Aided Design (ECAD) programs that enable developers to design, synthesize, optimize, and simulate the circuits at the RTL. Some of the tools allow developers to apply power saving techniques and/or modifications, such the sleep-mode transformation described above.
However, the tools generally require that the techniques and modifications be applied during the synthesis of the micro-electronic circuits, when the circuit has yet to be optimized and simulated. For example, when using the VHDL to apply the sleep-mode transformation technique to a circuit design, the tools require that the developer put pragmas—which are synthetic comments to direct the actions of the VHDL compiler—in the VHDL code to inform the compiler which functional blocks, such as the multiplier 40, to be put into sleep-mode.
This is done before any optimization or simulation is done. Thus, power consumption and timing—another important optimization metric—have to be estimated, which may cause some difficulty in the design process. Generally, faster performing circuits consume more power. Thus, in some instances, adding power saving techniques and/or modifications may cause the circuit to perform slower. If, after timing and logic optimization tools are applied, the timing requirement for design is violated, then either the tools have to undo the sleep-mode transformations to improve the timing, or in the worst case, the developer may have to manually fix the timing problems. But, if the timing and logic optimization tools are applied after the power saving techniques are applied, undoing the power saving techniques and/or modifications may not be a simple task.
One reason is because the timing of the circuit generally depends upon the timing of the critical paths within the circuit, which are the slowest paths that data must travel during circuit operation. The timing optimization tools primarily optimize the critical paths. Because the power saving techniques and/or modifications are applied to the circuit based on estimations instead of accurate information, the techniques and/or modifications may sometimes create critical paths that would not otherwise be critical paths but for the techniques and/or modifications. Thus, if the timing optimization tools operate after the power saving techniques and/or modifications are applied, then the optimization tools may optimize the wrong critical paths, i.e., critical paths created by the power saving techniques and/or modifications. When the timing optimization tools compensate for these wrong critical paths, the circuit may end up increasing the power consumption.
Further, undoing the technique and/or modification after optimization would be difficult in such a situation because the compensation done by the timing optimization tools would also have to be undone. A lot of time and effort would be wasted during the design and synthesis process.
The present invention provides a method and mechanism for applying power saving techniques and/or modifications to micro-electronic circuits. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques and/or modifications may be identified. Then, the one or more candidates may be marked within the micro-electronic circuit without materially modifying and/or committing the data and/or control paths of the circuit. Then, each power saving technique and/or modification applied to the one or more candidates may be evaluated to determine whether the technique and/or modification saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique and/or modification applied to the one or more candidates may be evaluated to determine whether the technique and/or modification is reducible, and if so, then the technique and/or modification may be reduced to determine whether such reduction improves the circuit's timing.
Further aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims.